1. Field of the Invention
The present invention relates to a phase comparator performing a phase comparison between two input signals within a signal processing circuit.
2. Description of the Background Art
In general, a PLL (phase-locked loop) circuit is in wide use for stabilizing the oscillation frequency, for example, of an oscillator.
The PLL circuit monitors such a reference signal as a system clock and establishes synchronization with another clock or the like. Specifically, a phase difference between a reference signal which is input to a phase comparator in the PLL circuit and an internal feedback signal is measured to adjust the oscillation frequency of a voltage-controlled oscillator (hereinafter referred to as VCO) which generates a timing signal according to the measured phase difference. The generated signal is input as a feedback signal to the phase comparator and the phase comparator makes a phase comparison again between the reference signal and the feedback signal.
The PLL circuit thus monitors the reference signal and continuously performs the above-described loop operation to adjust the oscillation frequency of the VCO circuit thereby synchronize respective phases of the reference signal and the feedback signal.
One of various types of phase comparators is, for example, a digital phase comparison circuit which performs a phase comparison based on the exclusive OR. Japanese Patent Laying-Open No. 2000-36729 discloses a configuration of a phase comparator performing a phase comparison based on time-average amounts of currents flown respectively into and out of the circuit according to the exclusive OR between two input signals.
Specifically, there are provided a logic circuit performing a switching operation based on the exclusive OR between two-input-signals and a current control circuit controlling the amounts of currents flown into and out of the circuit according to the result of the phase comparison.
If a phase comparison is made between signals in the high-frequency band, the logic circuit is required to perform signal processing at a higher frequency than that of input signals, i.e., to perform a high-speed switching operation.
The logic circuit, however, needs a predetermined period of time for passing electric charges for charging/discharging in the switching operation. Therefore, if an extremely high speed operation is required, the switching operation could not follow the change in phase. In other words, the amount of current controlled by the current control circuit could not follow the change in phase. For this reason, it is difficult for the conventional phase comparator to perform a highly accurate phase comparison when the comparator performs a phase comparison between signals in the high-frequency band.
An object of the present invention is to provide a phase comparator solving the above-described problem and capable of performing a stable phase comparison for the high-frequency band.
A phase comparator according to the present invention that detects a phase difference between a first signal and a second signal serving as a reference includes a retiming circuit and a phase comparison unit. The retiming circuit samples the first signal at a timing synchronized with the second signal to output a third signal. The phase comparison unit passes a current according to the phase difference based on the first, second and third signals. The phase comparison unit includes first and second current sources, an output node and first and second current control circuits. The first current control circuit is connected between the first current source and the output node and passes a current flown to the output node when a result of an exclusive OR operation between the first signal and the third signal is a first logic level. The second current control circuit is connected between the second current source and the output node and receives a current flown from the output node when the second signal has a second logic level opposite to the first logic level. The first current control circuit has two switching units connected between the first current source and the output node. The two switching units are designed to provide the first logic level as the result of the exclusive OR operation between the first signal and the third signal when at-least one of the two switching units is turned on according to a predetermined combination of the first signal and the third signal that are input.
According to the present invention as discussed above, two switching units are provided in the first current control circuit which supplies a current to the output node when the result of the exclusive OR between the first signal and the third signal is the first logic level. The two switching units are configured to provide the first logic level as the result of the exclusive OR when at least one of the switching units is turned on according to a predetermined combination of the first and third signals. Accordingly, without logical operation of the exclusive OR by, for example, a logic circuit, the switching operation by the two switching units is associated with the logical operation to perform similar processing. Then, a fast phase-comparison operation can be carried out.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.